/*
 * @file     g_sysctrl.h
 * @brief    This file contains all the functions prototypes for the sysctrl firmware library.
 *
 * Change Logs:
 * Date           Author             Version        Notes
 * 2021-05-19     dengzhiqian        V1.0.0         the first version
 * 2022-07-11      dengzhiqian        V1.0.2         add lightsleep paradef
 * 2022-07-21      dengzhiqian        V1.0.3         add exen config and iofp config in poweroff api
 */

#ifndef __G_SYSCTRL_H__
#define __G_SYSCTRL_H__

#ifdef __cplusplus
extern "C"
{
#endif

/* Includes ------------------------------------------------------------------*/
#include "g_1903.h"
#include "g_system.h"
#include "g_gpio.h"
#include "g_timer.h"
#include "g_bpu.h"
#include "g_vbat_ctr.h"
#include "g_otp.h"

/** @defgroup SYSCTRL_AHBPeriph_Types
 * @{
 */
#define SYSCTRL_AHBPeriph_RNG BIT0
#define SYSCTRL_AHBPeriph_QSPI BIT1
#define SYSCTRL_AHBPeriph_SHA BIT2
#define SYSCTRL_AHBPeriph_CRC BIT3
#define SYSCTRL_AHBPeriph_USB BIT6
#define SYSCTRL_AHBPeriph_SPI BIT7
#define SYSCTRL_AHBPeriph_DES BIT8
#define SYSCTRL_AHBPeriph_RSACTRL BIT9
#define SYSCTRL_AHBPeriph_AES BIT10
#define SYSCTRL_AHBPeriph_GPIO BIT11
#define SYSCTRL_AHBPeriph_SM4 BIT14
#define SYSCTRL_AHBPeriph_UART BIT15
#define SYSCTRL_AHBPeriph_7811 BIT16
#define SYSCTRL_AHBPeriph_7811_ADC BIT17
#define SYSCTRL_AHBPeriph_PSRAM BIT19
#define SYSCTRL_AHBPeriph_HSPI BIT20
#define SYSCTRL_AHBPeriph_DAC BIT21
#define SYSCTRL_AHBPeriph_DCMI BIT22
#define SYSCTRL_AHBPeriph_SDIO BIT23
#define SYSCTRL_AHBPeriph_CP192M BIT24
#define IS_SYSCTRL_AHB_PERIPH(PERIPH) ((PERIPH & 0x1ffcfcc) != 0x00)

/** @defgroup SYSCTRL_APBPeriph_Types
 * @{
 */
#define SYSCTRL_APBPeriph_PWM BIT4
#define SYSCTRL_APBPeriph_WDT BIT5
#define SYSCTRL_APBPeriph_7816CTRL BIT12
#define SYSCTRL_APBPeriph_7816CTRL_2 BIT13
#define IS_SYSCTRL_APB_PERIPH(PERIPH) ((PERIPH & 0x3030) != 0x00)

/** @defgroup SYSCTRL_RVPeriph_Types
 * @{
 */
#define SYSCTRL_RVPeriph_MEMCP BIT25
#define SYSCTRL_RVPeriph_MPU_DMA BIT26
#define SYSCTRL_RVPeriph_RV_SYS BIT27
#define SYSCTRL_RVPeriph_RV_REG BIT28
#define IS_SYSCTRL_RV_PERIPH(PERIPH) ((PERIPH & 0x3030) != 0x00)

/** @defgroup G_SYSCTRL_RC48MPeriph_Types
 * @{
 */
#define SYSCTRL_RC48MMPeriph BIT29

    /** @defgroup G_SYSCTRL_PLLCrystal_Types
     * @{
     */
    typedef enum
    {
        XTAL_MODE,
        OUTSIZE_MODE,
    } G_SYSCTRL_PLLCrystal_TypeDef;

    /** @defgroup Sysctrl_Clock_Frequency_Def
     * @{
     */

    typedef enum
    {
        PLL_CHANNEL_48MHz = (1 << 0),
        PLL_CHANNEL_192MHz = (1 << 1),
        PLL_CHANNEL_256MHz = (1 << 2),
        PLL_CHANNEL_IGNORE = (1 << 3)
    } G_SYSCTRL_PLLChannel_TypeDef;

#define IS_SYSCTRL_MAXPLL_SELECT(PREQ) ((PREQ == HSEPLL_48MHz) ||  \
                                        (PREQ == HSEPLL_160MHz) || \
                                        (PREQ == HSEPLL_192MHz) || \
                                        (PREQ == HSEPLL_224MHz) || \
                                        (PREQ == HSEPLL_256MHz))

#define CLOCK_FRE_BASE (1000000)
#define CLOCk_FRE_1K (1000)
#define CLOCK_FRE_32K (32 * 1000)
#define CLOCk_FRE_1M (1 * CLOCK_FRE_BASE)
#define CLOCK_FRE_48M (48 * CLOCK_FRE_BASE)
#define CLOCK_FRE_96M (96 * CLOCK_FRE_BASE)
#define CLOCK_FRE_120M (120 * CLOCK_FRE_BASE)
#define CLOCK_FRE_144M (144 * CLOCK_FRE_BASE)
#define CLOCK_FRE_168M (168 * CLOCK_FRE_BASE)
#define CLOCK_FRE_192M (192 * CLOCK_FRE_BASE)
#define CLOCK_FRE_224M (224 * CLOCK_FRE_BASE)
#define CLOCK_FRE_256M (256 * CLOCK_FRE_BASE)
#define CLOCK_FRE_384M (384 * CLOCK_FRE_BASE)

    typedef enum
    {
        MCU_FRE = 0,
        PER1_AHB_FRE,
        PER1_QSPI_FRE,
        PER2_HSPI_FRE,
        PER2_PSRAM_FRE,
        PER3_ICE_FRE,
        PER3_ADAC_FRE,
        PER3_GPIO0_FRE,
        PER3_GPIO1_FRE,
        RSA_FRE,
        PCLK_FRE
    } G_SYSCTRL_Exported_Types;

#define IS_SYSCTRL_EXPORTED_TYPES(TYPES) ((TYPES == MCU_FRE) ||        \
                                          (TYPES == PER1_AHB_FRE) ||   \
                                          (TYPES == PER1_QSPI_FRE) ||  \
                                          (TYPES == PER2_HSPI_FRE) ||  \
                                          (TYPES == PER2_PSRAM_FRE) || \
                                          (TYPES == PER3_ICE_FRE) ||   \
                                          (TYPES == PER3_ADAC_FRE) ||  \
                                          (TYPES == PER3_GPIO0_FRE) || \
                                          (TYPES == PER3_GPIO1_FRE) || \
                                          (TYPES == RSA_FRE) ||        \
                                          (TYPES == PCLK_FRE))
    typedef struct
    {
        uint8_t Source;
        uint8_t PllSource;
        uint8_t divsel;
        uint8_t div_hi;
        uint8_t div_lo;
    } G_SYSCTRL_ClocksFreParaTypeDef;

/** @defgroup G_SYSCTRL_PLL_SEL_Types
 * @{
 */
#define RC_192M (0xAA)
#define PLL_HSI (0xA)
#define PLL_HSE (0x5)
#define IS_SYSCTRL_PLL_SEL(PllSource) ((PllSource == RC_192M) || (PllSource == PLL_HSI) || (PllSource == PLL_HSE))

    /** @defgroup HCLK_PERIPH_SEL_Types
     * @{
     */
    typedef enum
    {
        RC192_48M = 0,
        HSI48M,
        HSE48M,
    } G_HCLK_Select;
#define IS_SYSCTRL_HCLK_SELECT(PERIPH) ((PERIPH == RC192_48M) || \
                                        (PERIPH == HSI48M) ||    \
                                        (PERIPH == HSE48M))

#define IS_SYSCTRL_MCU_RANDMASK(mask) ((mask & 0xf0) == 0)
#define IS_SYSCTRL_RSA_RANDMASK(mask) ((mask & 0xf0) == 0)

    /** @defgroup MCUCLK_SOURCE_SEL_Types
     * @{
     */
    typedef enum
    {
        MCU_RC192M = 0,
        MCU_PLL_OUT_NORM,
        MCU_PLL_OUT_MAX,
        MCU_PLL_OUT_FIXED,
        MCU_RC32K,
    } G_SYSCLK_MCUSource_TypeDef;

#define IS_SYSCTRL_MCUSOURCE_SEL(SOURCE) ((SOURCE == (G_SYSCLK_MCUSource_TypeDef)MCU_RC192M) ||        \
                                          (SOURCE == (G_SYSCLK_MCUSource_TypeDef)MCU_PLL_OUT_NORM) ||  \
                                          (SOURCE == (G_SYSCLK_MCUSource_TypeDef)MCU_PLL_OUT_MAX) ||   \
                                          (SOURCE == (G_SYSCLK_MCUSource_TypeDef)MCU_PLL_OUT_FIXED) || \
                                          (SOURCE == (G_SYSCLK_MCUSource_TypeDef)MCU_RC32K))

#define IS_SYSCTRL_MCUPLLSOURCE(SOURCE) (SOURCE == (G_SYSCLK_MCUSource_TypeDef)MCU_PLL_OUT_NORM) ||    \
                                            (SOURCE == (G_SYSCLK_MCUSource_TypeDef)MCU_PLL_OUT_MAX) || \
                                            (SOURCE == (G_SYSCLK_MCUSource_TypeDef)MCU_PLL_OUT_FIXED)

#define IS_MCU_PLLSOURCE(PLLSELECT, SOURCE)       \
    if (PLLSELECT != RC_192M)                     \
    {                                             \
        _ASSERT(IS_SYSCTRL_MCUPLLSOURCE(SOURCE)); \
    }

#define IS_MCU_PLLCHANNEL(SOURCE, PLLCHANNEL) \
    if (SOURCE == MCU_PLL_OUT_NORM)           \
    {                                         \
        PLLCHANNEL = PLL_CHANNEL_192MHz;      \
    }                                         \
    else if (SOURCE == MCU_PLL_OUT_MAX)       \
    {                                         \
        PLLCHANNEL = PLL_CHANNEL_256MHz;      \
    }                                         \
    else if (SOURCE == MCU_PLL_OUT_FIXED)     \
    {                                         \
        PLLCHANNEL = PLL_CHANNEL_48MHz;       \
    }

#define G_GET_MCU_SOURCE_FREQ(SOURCE, FREQ)                   \
    if (SOURCE == MCU_PLL_OUT_NORM || SOURCE == MCU_RC192M) \
    {                                                       \
        FREQ = CLOCK_FRE_192M;                              \
    }                                                       \
    else if (SOURCE == MCU_PLL_OUT_MAX)                     \
    {                                                       \
        FREQ = CLOCK_FRE_256M;                              \
    }                                                       \
    else if (SOURCE == MCU_PLL_OUT_FIXED)                   \
    {                                                       \
        FREQ = CLOCK_FRE_48M;                               \
    }                                                       \
    else if (SOURCE == MCU_RC32K)                           \
    {                                                       \
        FREQ = CLOCK_FRE_32K;                               \
    }

    /** @defgroup PER1CLK_SOURCE_SEL_Types
     * @{
     */
    typedef enum
    {
        PER1_CLKMCU = 0,
        PER1_RC192M,
        PER1_PLL_OUT_NORM,
        PER1_PLL_OUT_FIXED,
    } G_SYSCLK_PER1Source_TypeDef;

#define IS_SYSCTRL_PER1SOURCE_SEL(SOURCE) ((SOURCE == (G_SYSCLK_PER1Source_TypeDef)PER1_CLKMCU) ||       \
                                           (SOURCE == (G_SYSCLK_PER1Source_TypeDef)PER1_RC192M) ||       \
                                           (SOURCE == (G_SYSCLK_PER1Source_TypeDef)PER1_PLL_OUT_NORM) || \
                                           (SOURCE == (G_SYSCLK_PER1Source_TypeDef)PER1_PLL_OUT_FIXED))

#define IS_SYSCTRL_PER1PLLSOURCE(SOURCE) (SOURCE == (G_SYSCLK_PER1Source_TypeDef)PER1_PLL_OUT_NORM) || \
                                             (SOURCE == (G_SYSCLK_PER1Source_TypeDef)MCU_PLL_OUT_FIXED)

#define IS_PER1_PLLSOURCE(PLLSELECT, SOURCE)       \
    if (PLLSELECT != RC_192M)                      \
    {                                              \
        _ASSERT(IS_SYSCTRL_PER1PLLSOURCE(SOURCE)); \
    }

#define IS_PER1_PLLCHANNEL(SOURCE) (SOURCE == PER1_PLL_OUT_NORM ? (PLL_CHANNEL_192MHz) : (PLL_CHANNEL_48MHz))

    /** @defgroup PER2CLK_SOURCE_SEL_Types
     * @{
     */
    typedef enum
    {
        PER2_CLKMCU = 0,
        PER2_RC192M,
        PER2_PLL_OUT_NORM,
        PER2_PLL_OUT_MAX,
    } G_SYSCLK_PER2Source_TypeDef;

#define IS_SYSCTRL_PER2SOURCE_SEL(SOURCE) ((SOURCE == PER2_CLKMCU) ||       \
                                           (SOURCE == PER2_RC192M) ||       \
                                           (SOURCE == PER2_PLL_OUT_NORM) || \
                                           (SOURCE == PER2_PLL_OUT_MAX))

#define IS_SYSCTRL_PER2PLLSOURCE(SOURCE) (SOURCE == PER2_PLL_OUT_NORM) || \
                                             (SOURCE == PER2_PLL_OUT_MAX)

#define IS_PER2_PLLSOURCE(PLLSELECT, SOURCE)       \
    if (PLLSELECT != RC_192M)                      \
    {                                              \
        _ASSERT(IS_SYSCTRL_PER2PLLSOURCE(SOURCE)); \
    }

#define IS_PER2_PLLCHANNEL(SOURCE) (SOURCE == PER2_PLL_OUT_NORM ? (PLL_CHANNEL_192MHz) : (PLL_CHANNEL_256MHz))

/** @defgroup G_SYSCTRL_CLK_DIV_Types
 * @{
 */
#define SYSCTRL_CLK_Div_None ((uint32_t)0xFF)
#define SYSCTRL_CLK_Div2 ((uint32_t)0x00)
#define SYSCTRL_CLK_Div3 ((uint32_t)0x01)
#define SYSCTRL_CLK_Div4 ((uint32_t)0x02)
#define SYSCTRL_CLK_Div5 ((uint32_t)0x03)
#define SYSCTRL_CLK_Div6 ((uint32_t)0x04)
#define SYSCTRL_CLK_Div7 ((uint32_t)0x05)
#define SYSCTRL_CLK_Div8 ((uint32_t)0x06)
#define SYSCTRL_CLK_Div9 ((uint32_t)0x07)
#define SYSCTRL_CLK_Div10 ((uint32_t)0x08)
#define SYSCTRL_CLK_Div11 ((uint32_t)0x09)
#define SYSCTRL_CLK_Div12 ((uint32_t)0x0a)
#define SYSCTRL_CLK_Div13 ((uint32_t)0x0b)
#define SYSCTRL_CLK_Div14 ((uint32_t)0x0c)
#define SYSCTRL_CLK_Div15 ((uint32_t)0x0d)
#define SYSCTRL_CLK_Div16 ((uint32_t)0x0e)
#define SYSCTRL_CLK_Div17 ((uint32_t)0x0f)
#define SYSCTRL_CLK_Div18 ((uint32_t)0x10)
#define SYSCTRL_CLK_Div19 ((uint32_t)0x11)
#define SYSCTRL_CLK_Div20 ((uint32_t)0x12)
#define SYSCTRL_CLK_Div21 ((uint32_t)0x13)
#define SYSCTRL_CLK_Div22 ((uint32_t)0x14)
#define SYSCTRL_CLK_Div23 ((uint32_t)0x15)
#define SYSCTRL_CLK_Div24 ((uint32_t)0x16)
#define SYSCTRL_CLK_Div25 ((uint32_t)0x17)
#define SYSCTRL_CLK_Div26 ((uint32_t)0x18)
#define SYSCTRL_CLK_Div27 ((uint32_t)0x19)
#define SYSCTRL_CLK_Div28 ((uint32_t)0x1a)
#define SYSCTRL_CLK_Div29 ((uint32_t)0x1b)
#define SYSCTRL_CLK_Div30 ((uint32_t)0x1c)
#define SYSCTRL_CLK_Div31 ((uint32_t)0x1d)
#define SYSCTRL_CLK_Div32 ((uint32_t)0x1e)
#define IS_SYSCTRL_CLK_DIV(div) ((div & 0xe0) == 0 || div == 0xFF)

/** @defgroup G_SYSCTRL_PER1_DIV_Types
 * @{
 */
#define SYSCTRL_PER1_Div2 ((uint32_t)0x00)
#define SYSCTRL_PER1_Div3 ((uint32_t)0x01)
#define SYSCTRL_PER1_Div4 ((uint32_t)0x02)
#define SYSCTRL_PER1_Div5 ((uint32_t)0x03)
#define SYSCTRL_PER1_Div6 ((uint32_t)0x04)
#define SYSCTRL_PER1_Div7 ((uint32_t)0x05)
#define SYSCTRL_PER1_Div8 ((uint32_t)0x06)
#define SYSCTRL_PER1_Div9 ((uint32_t)0x07)
#define SYSCTRL_PER1_Div10 ((uint32_t)0x08)
#define SYSCTRL_PER1_Div11 ((uint32_t)0x09)
#define SYSCTRL_PER1_Div12 ((uint32_t)0x0a)
#define SYSCTRL_PER1_Div13 ((uint32_t)0x0b)
#define SYSCTRL_PER1_Div14 ((uint32_t)0x0c)
#define SYSCTRL_PER1_Div15 ((uint32_t)0x0d)
#define SYSCTRL_PER1_Div16 ((uint32_t)0x0e)
#define SYSCTRL_PER1_Div17 ((uint32_t)0x0f)
#define SYSCTRL_PER1_Div18 ((uint32_t)0x10)
#define SYSCTRL_PER1_Div19 ((uint32_t)0x11)
#define SYSCTRL_PER1_Div20 ((uint32_t)0x12)
#define SYSCTRL_PER1_Div21 ((uint32_t)0x13)
#define SYSCTRL_PER1_Div22 ((uint32_t)0x14)
#define SYSCTRL_PER1_Div23 ((uint32_t)0x15)
#define SYSCTRL_PER1_Div24 ((uint32_t)0x16)
#define SYSCTRL_PER1_Div25 ((uint32_t)0x17)
#define SYSCTRL_PER1_Div26 ((uint32_t)0x18)
#define SYSCTRL_PER1_Div27 ((uint32_t)0x19)
#define SYSCTRL_PER1_Div28 ((uint32_t)0x1a)
#define SYSCTRL_PER1_Div29 ((uint32_t)0x1b)
#define SYSCTRL_PER1_Div30 ((uint32_t)0x1c)
#define SYSCTRL_PER1_Div31 ((uint32_t)0x1d)
#define SYSCTRL_PER1_Div32 ((uint32_t)0x1e)
#define IS_SYSCTRL_PER1_DIV(div) ((div & 0xe0) == 0)

    /** @defgroup PER3CLK_SOURCE_SEL_Types
     * @{
     */
    typedef enum
    {
        RC48M = 0,
        PLL_HSI_48M,
        PLL_HSE_48M,
    } G_PER3CLK_Source_TypeDef;
#define IS_PER3CTRL_SOURCE_SEL(SOURCE) ((SOURCE == RC48M) ||       \
                                        (SOURCE == PLL_HSI_48M) || \
                                        (SOURCE == PLL_HSE_48M))

/** @defgroup G_SYSCTRL_PER3_DIV_Types
 * @{
 */
#define SYSCTRL_PER3_Div2 ((uint32_t)0x00)
#define SYSCTRL_PER3_Div3 ((uint32_t)0x01)
#define SYSCTRL_PER3_Div4 ((uint32_t)0x02)
#define SYSCTRL_PER3_Div5 ((uint32_t)0x03)
#define SYSCTRL_PER3_Div6 ((uint32_t)0x04)
#define SYSCTRL_PER3_Div7 ((uint32_t)0x05)
#define SYSCTRL_PER3_Div8 ((uint32_t)0x06)
#define SYSCTRL_PER3_Div9 ((uint32_t)0x07)
#define IS_SYSCTRL_PER3_DIV(div) ((div & 0xf0) == 0)

    /** @defgroup G_SYSCTRL_DeepSleepWakeSrcType
     * @{
     */
    typedef enum
    {
        GPIO_SRC = 1 << 0,   /*Gpio Levle Wakeup*/
        LSERTC_SRC = 1 << 1, /*Lse Rtc Second interrupt or timed interrupt Wakeup*/
        LSIRTC_SRC = 1 << 2, /*Lsi Rtc Second interrupt or timed interrupt Wakeup*/
        SEC_SRC = 1 << 3,    /*Security event wakeup */
        HCHGR_SRC = 1 << 4,  /*Chgr high level event*/
        LCHGR_SRC = 1 << 5,  /*Chgr low level event*/
        POWKEY_SRC = 1 << 6  /*Powerkey level event*/
    } G_SYSCTRL_DeepSleepWakeSrcType;

    /** @defgroup G_SYSCTRL_DeepSleepWakeLevel
     * @{
     */
    typedef enum
    {
        HIGH_WAKEUP  = 0,   /*High Level Wakeup*/
        LOW_WAKEUP   = 1,   /*Low Level Wakeup*/
        ALONE_WAKEUP = 0x100 /*gpio Set wake level independently*/
    } G_SYSCTRL_DeepSleepWakeLevel;

    /** @defgroup G_SYSCTRL_DeepSleepChgrEventType
     * @{
     */
    typedef enum
    {
        S_VBAT_LV = 1 << 0,
        S_RCH_EN = 1 << 1,
        S_IND = 1 << 2,
        S_ICHG = 1 << 3,
        S_REST = 1 << 4,
        S_UVLO_OK_AON = 1 << 5,
        S_PGOOD = 1 << 6,
        S_DPPM_OV_CV = 1 << 7,
        S_DPPM_OV_CC = 1 << 8,
        S_CC_OV_CV = 1 << 9,
        S_DET_AON = 1 << 10,
        S_VBAT_OV = 1 << 11
    } G_SYSCTRL_DeepSleepChgrEventType;
    
    /** @defgroup G_SYSCTRL_LpmRecoverTypeDef
     * @{
     */
    typedef enum
    {
        RECOVER_PD = 0,
        RECOVER_PU,
        RECOVER_OUTPUT_LOW,
        RECOVER_OUTPUT_HIGH
    }G_SYSCTRL_LpmRecoverTypeDef;

    /** @defgroup G_SYSCTRL_DeepSleepWakeSrcParaDef
     * @{
     */
    typedef struct
    {
        uint32_t SrcType;                            /*Wakeup Src Type for G_SYSCTRL_DeepSleepWakeSrcType*/
        G_SYSCTRL_DeepSleepWakeLevel Powkey_WakeLevel; /*Powerkey Wakeup Level*/
        G_SYSCTRL_DeepSleepWakeLevel Gpio_WakeupLevel; /*Gpio Wakeup Level*/
        uint32_t Gpio_Pin0_Pin31;                    /*bit0~bit31 write 1 correspond gpio0 ~gpio31 enable (low) wakeup*/
        uint32_t Gpio_Pin32_Pin63;                   /*bit0~bit31 write 1 correspond gpio32 ~gpio63 enable (low) wakeup*/
        uint32_t Gpio_Pin64_Pin79;                   /*bit0~bit15 write 1 correspond gpio64 ~gpio79 enable (low) wakeup*/
        uint32_t Chgr_HighWakeEvent;                 /*chgr high level wakeup event  for G_SYSCTRL_DeepSleepChgrEventType*/
        uint32_t Chgr_LowWakeEvent;                  /*chgr low level wakeup event  for G_SYSCTRL_DeepSleepChgrEventType*/
        uint32_t Gpio_HiWkEn_Pin0_Pin31;             /*bit0~bit31 write 1 correspond gpio0 ~gpio31 enable high wakeup*/
        uint32_t Gpio_HiWkEn_Pin32_Pin63;            /*bit0~bit31 write 1 correspond gpio32 ~gpio63 enable high wakeup*/
        uint32_t Gpio_HiWkEn_Pin64_Pin79;            /*bit0~bit15 write 1 correspond gpio64 ~gpio79 enable high wakeup*/
    } G_SYSCTRL_DeepSleepWakeSrcParaDef;

    /** @defgroup G_SYSCTRL_LightSleepParaDef
     * @{
     */
    typedef struct
    {
        uint32_t PD_Unusedio[3]; /*bit0~bit79 correspond gpio64 ~gpio79*/
        uint32_t PU_Unusedio[3];
    } G_SYSCTRL_LightSleepParaDef;

    void G_SYSCTRL_AHBPeriphClockCmd(uint32_t G_SYSCTRL_AHBPeriph, G_FunctionalState NewState);
    void G_SYSCTRL_APBPeriphClockCmd(uint32_t G_SYSCTRL_APBPeriph, G_FunctionalState NewState);
    void G_SYSCTRL_RC48MPeriphClockCmd(G_FunctionalState NewState);
    void G_SYSCTRL_HCLKPeriphSelect(uint32_t Periph, G_HCLK_Select Select);
    void G_SYSCTRL_MCUClkRandCmd(G_FunctionalState NewState);
    void G_SYSCTRL_MCUClkRandMask(uint8_t randmask);
    void G_SYSCTRL_PLLCrystalConfig(G_SYSCTRL_PLLCrystal_TypeDef Mode, uint32_t OscFreq);
    void G_SYSCTRL_PLLFreqConfig(uint8_t PllSource, uint8_t PllFreq);
    void G_SYSCTRL_PLLOpen(uint8_t PllSource, uint8_t PLLChannel);
    void G_SYSCTRL_PLLClose(uint8_t PllSource, uint8_t PLLChannel);
    void G_SYSCTRL_PLLDeInit(uint8_t PllSource);
    void G_SYSCTRL_MCUClkCtrl(uint8_t PllSource, G_SYSCLK_MCUSource_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_PER1AhbClkCtrl(uint8_t PllSource, G_SYSCLK_PER1Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_PER1QspiClkCtrl(uint8_t PllSource, G_SYSCLK_PER1Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_PER2PsramClkCtrl(uint8_t PllSource, G_SYSCLK_PER2Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_PER2HspiClkCtrl(uint8_t PllSource, G_SYSCLK_PER2Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_PER3IceClkCtrl(G_PER3CLK_Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_PER3AdacClkCtrl(G_PER3CLK_Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_PER3Gpio0ClkCtrl(G_PER3CLK_Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_PER3Gpio1ClkCtrl(G_PER3CLK_Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_RSAClkCtrl(uint8_t PllSource, G_SYSCLK_PER2Source_TypeDef Source, uint32_t Clk_Div);
    void G_SYSCTRL_LightSleep(G_SYSCTRL_LightSleepParaDef *Para);
    void G_SYSCTRL_DeepSleep(void);
    void G_SYSCTRL_LightSleepWakeSrcIT(uint32_t WakeSource, G_FunctionalState NewState);
    void G_SYSCTRL_DeepSleepWakeSrcIT(G_SYSCTRL_DeepSleepWakeSrcParaDef *WakeSrcPara);
    uint32_t G_SYSCTRL_GetClocksFreq(G_SYSCTRL_Exported_Types Clocks_Types);
    void G_SYSCTRL_SoftReset(void);
    void G_SYSCTRL_HvldoOcpSel(G_Boolean Ocp_En);
    void G_SYSCTRL_PowerOff(void);
    G_Boolean G_SYSCTRL_SetWakeupRecoverGpio(uint8_t index,G_GPIO_TypeDef GPIOx, G_GPIO_Pin_TypeDef GPIO_Pin,G_SYSCTRL_LpmRecoverTypeDef type);

#ifdef __cplusplus
}
#endif

#endif

/************************ (C) COPYRIGHT GKT *****END OF FILE****/
